`timescale 1ns / 10ps
`define clock_period 20

module factorial_demo_tb;

	reg clk;
	reg[3:0] n;
	wire[31:0] result;

	factorial_demo demo0(
		.Clk(clk),
		.N(n),      
		.Result(result) 
	);
	
	always #(`clock_period / 2) clk = ~clk;
	
	initial begin
	
		clk = 1'b0;
		n = 4'd4;
		#(`clock_period)
		
		n = 4'd7;
		#(`clock_period)
		
		$stop;
	
	end

endmodule
